1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to an addressing scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices.
2. Description of the Related Art
There is a demand for faster, higher capacity, random access memory (RAM) devices. RAM devices, such as dynamic random access memory (DRAM) are typically used as the main memory in computer systems. Although the operating speed of the DRAM has improved over the years, the speed has not reached that of the processors used to access the DRAM. In a computer system, for example, the slow access and cycle times of the DRAM lead to system bottlenecks. These bottlenecks slow down the throughput of the system despite the very fast operating speed of the system's processor.
A newer type of memory known as a synchronous dynamic random access memory (SDRAM) has been developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the system clock. That is, input and output data of the SDRAM are synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.
Some SDRAMs are capable of synchronously providing burst data at a high-speed data rate by automatically generating a column addresses for a memory array of storage cells organized as rows and columns. In addition, some SDRAMs utilize two or more banks of memory arrays which permits interleaving data betveen the banks to reduce access times and increase the speed of the memory.
Although SDRAMs have overcome disadvantages of the other memory devices, such as DRAMs, there is still a need for faster memory devices. Double data rate (DDR) SDRAMs are being developed to provide twice the operating speed of the conventional SDRAM. These devices allow data transfers on both the rising and falling edges of the system clock and thus, provide twice as much data as the conventional SDRAM. DDR SDRAMs are also capable of providing burst data at a high-speed data rate.
Although DDR SDRAMs provide speedier operation times, they typically involve complicated addressing schemes and circuitry in order to synchronize the data access and transfers occurring on both the rising and falling edges of the system clock. Accordingly, there is a desire and need for a simplified addressing scheme of a DDR SDRAM.